Time constrained verification of analog circuits using model-checking algorithms
- In this contribution we present algorithms for model checking of analog circuits enabling the specification of time constraints. Furthermore, a methodology for defining time-based specifications is introduced. An already known method for model checking of integrated analog circuits has been extended to take into account time constraints. The method will be presented using three industrial circuits. The results of model checking will be compared to verification by simulation.
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| Author: | Darius Grabowski, Daniel Platte, Lars HedrichGND, Erich BarkeORCiDGND |
|---|---|
| URN: | urn:nbn:de:hebis:30:3-762646 |
| DOI: | https://doi.org/10.1016/j.entcs.2006.01.026 |
| ISSN: | 1571-0661 |
| Parent Title (English): | Electronic notes in theoretical computer science |
| Publisher: | Elsevier |
| Place of publication: | Amsterdam |
| Document Type: | Article |
| Language: | English |
| Date of Publication (online): | 2006/06/07 |
| Date of first Publication: | 2006/06/07 |
| Publishing Institution: | Universitätsbibliothek Johann Christian Senckenberg |
| Release Date: | 2023/12/29 |
| Tag: | Analog Circuits; CTL; Model Checking; Time Constraints |
| Volume: | 153 |
| Issue: | 3 |
| Page Number: | 16 |
| First Page: | 37 |
| Last Page: | 52 |
| HeBIS-PPN: | 516360299 |
| Institutes: | Informatik und Mathematik / Informatik |
| Dewey Decimal Classification: | 0 Informatik, Informationswissenschaft, allgemeine Werke / 00 Informatik, Wissen, Systeme / 004 Datenverarbeitung; Informatik |
| Sammlungen: | Universitätspublikationen |
| Licence (German): |  Creative Commons - CC BY-NC-ND - Namensnennung - Nicht kommerziell - Keine Bearbeitungen 4.0 International |
