TY  - JOUR
A1  - Stoffel, Dominik
A1  - Kunz, Wolfgang
T1  - Verification of integer multipliers on the arithmetic bit level
T2  - Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, (ICCAD) Nov. 2001, San Jose CA, USA
N2  - One of the most severe short-comings of currently available equivalence checkers is their inability to verify integer multipliers. In this paper, we present a bit level reverse-engineering technique that can be integrated into standard equivalence checking flows. We propose a Boolean mapping algorithm that extracts a network of half adders from the gate netlist of an addition circuit. Once the arithmetic bit level representation of the circuit is obtained, equivalence checking can be performed using simple arithmetic operations. Experimental results show the promise of our approach.
Y1  - 2006
UR  - http://publikationen.ub.uni-frankfurt.de/frontdoor/index/index/docId/2886
UR  - https://nbn-resolving.org/urn:nbn:de:hebis:30-25206
SN  - 0-7803-7249-2
SP  - 183
EP  - 189
ER  -