Verification of integer multipliers on the arithmetic bit level

One of the most severe short-comings of currently available equivalence checkers is their inability to verify integer multipliers. In this paper, we present a bit level reverse-engineering technique that can be integrate
One of the most severe short-comings of currently available equivalence checkers is their inability to verify integer multipliers. In this paper, we present a bit level reverse-engineering technique that can be integrated into standard equivalence checking flows. We propose a Boolean mapping algorithm that extracts a network of half adders from the gate netlist of an addition circuit. Once the arithmetic bit level representation of the circuit is obtained, equivalence checking can be performed using simple arithmetic operations. Experimental results show the promise of our approach.
show moreshow less

Download full text files

Export metadata

  • Export Bibtex
  • Export RIS

Additional Services

    Share in Twitter Search Google Scholar
Metadaten
Author:Dominik Stoffel, Wolfgang Kunz
URN:urn:nbn:de:hebis:30-25206
ISBN:0-7803-7249-2
Parent Title (German):Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, (ICCAD) Nov. 2001, San Jose CA, USA
Document Type:Article
Language:English
Date of Publication (online):2006/03/21
Year of first Publication:2001
Publishing Institution:Universitätsbibliothek Johann Christian Senckenberg
Release Date:2006/03/21
First Page:183
Last Page:189
Source:Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, (ICCAD) Nov. 2001, San Jose CA, USA, Pages: 183 - 189 ; ©2001 IEEE ; ISBN:0-7803-7249-2
HeBIS PPN:226076571
Institutes:Informatik
Dewey Decimal Classification:004 Datenverarbeitung; Informatik
Sammlungen:Universitätspublikationen
Licence (German):License Logo Veröffentlichungsvertrag für Publikationen

$Rev: 11761 $