Article
96 search hits
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Studienwahl mit Verstand : mit Self-Assessment online die Eignung testen
(2007)
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Alexander Tillmann
Ashraf Abu Baker
Detlef Krömker
- Die Erwartungen von Studieninteressierten weichen häufig beträchtlich von den tatsächlichen Studieninhalten und Anforderungen ab. Ein Grund dafür ist, dass viele sich nicht genügend Klarheit verschaffen, welche eigenen Stärken und Schwächen für den Erfolg in Studium und Beruf »tatsächlich« relevant sind. So könnte zum Beispiel ein Abiturient mit guten Noten in Mathematik und Physik und mäßigen Zensuren in Deutsch und Englisch noch schlussfolgern, dass ihm »das Naturwissenschaftliche mehr liegt«. Ob das naturwissenschaftliche Verständnis für ein erfolgreiches Studium der Informatik jedoch gut genug ausgeprägt ist, lässt sich nicht so leicht erschließen. Noch schwieriger ist es für Studieninteressierte einzuschätzen, wie ihre »Soft Skills« ausgeprägt sind – also die Persönlichkeitsmerkmale, die in der Schule nicht systematisch beurteilt werden, jedoch hochgradig aussagekräftig für langfristigen Erfolg in Studium und Beruf sind. Ein Wechsel des Studienfaches zu Beginn des Studiums führt häufig zu einer Verlängerung der Studiendauer. Auch wenn eine derartige »Orientierungsphase« oftmals als normal und wichtig eingeschätzt wird, zeigt die praktische Erfahrung, dass Studierende mit kurzer Studiendauer jenen, die länger studiert haben, bei der Stellenvergabe tendenziell vorgezogen werden. Eine längere Studiendauer wird von Arbeitgebern häufig als Zeichen mangelnder Zielstrebigkeit oder fehlender Berufsmotivation interpretiert und kann sich so Chancen mindernd für Berufseinsteiger auswirken. Ebenso ist es im Interesse der Universitäten, die Zahl der Studienfachwechsel und -abbrüche so gering wie möglich zu halten – nicht zuletzt aus wirtschaftlichen Gründen. Deshalb bietet die Universität Frankfurt Studieninteressierten – zunächst in den Fächern Informatik und Psychologie – mit dem Self-Assessment konkrete Entscheidungshilfen an. Der verfolgte Ansatz zielt darauf ab, Abiturientinnen und Abiturienten möglichst frühzeitig und mit vertretbarem Aufwand die Möglichkeit zu bieten, selbst zu überprüfen, inwieweit ihre Erwartungen an einen Studiengang mit den tatsächlichen Inhalten und Anforderungen übereinstimmen. Das Konzept zur Erstellung eines Self-Assessments, das hier beispielhaft für den Studiengang Informatik vorgestellt wird, entstand nicht umsonst in enger Kooperation mit dem Institut für Psychologie (Prof. Dr. Helfried Moosbrugger, Dr. Siegbert Reiß, Ewa Jonkisz). Denn neben der fachlichen Qualifikation entscheiden über den Studienerfolg auch persönliche Eigenschaften wie Leistungsbereitschaft und Hartnäckigkeit. Die Auswertung des anonym durchgeführten Self-Assessments deckt außerdem Wissenslücken bei den Studieninteressierten auf, so dass eine gezielte Vorbereitung auf das Studium möglich wird. Zum Beispiel bietet der Fachbereich Mathematik und Informatik gezielte Vorbereitungskurse für Studienanfänger an, und zwar in Programmierung und Mathematik. Auch werden in den Semesterferien Repetitorien und Vorbereitungskurse angeboten – alles aus Studienbeiträgen finanziert. Auf diese Weise kann es zu einem homogeneren Kenntnisstand speziell bei den Studierenden im ersten Semester kommen. Ziel ist es, dadurch auch den »Erstsemesterschock « zu mildern. Das Online-Beratungsangebot trägt damit zu einer direkten Verbesserung der Lern- und Lehrsituation bei.
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Probabilistic and nondeterministic unary automata
(2003)
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Gregor Gramlich
- We investigate unary regular languages and compare deterministic finite automata (DFA’s), nondeterministic finite automata (NFA’s) and probabilistic finite automata (PFA’s) with respect to their size. Given a unary PFA with n states and an e-isolated cutpoint, we show that the minimal equivalent DFA has at most n exp 1/2e states in its cycle. This result is almost optimal, since for any alpha < 1 a family of PFA’s can be constructed such that every equivalent DFA has at least n exp alpha/2e states. Thus we show that for the model of probabilistic automata with a constant error bound, there is only a polynomial blowup for cyclic languages. Given a unary NFA with n states, we show that efficiently approximating the size of a minimal equivalent NFA within the factor sqrt(n)/ln n is impossible unless P = NP. This result even holds under the promise that the accepted language is cyclic. On the other hand we show that we can approximate a minimal NFA within the factor ln n, if we are given a cyclic unary n-state DFA.
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Analysis of a biologically-inspired system for real-time object recognition
(2005)
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Erik Murphy-Chutorian
Sarah Aboutalib
Jochen Triesch
- We present a biologically-inspired system for real-time, feed-forward object recognition in cluttered scenes. Our system utilizes a vocabulary of very sparse features that are shared between and within different object models. To detect objects in a novel scene, these features are located in the image, and each detected feature votes for all objects that are consistent with its presence. Due to the sharing of features between object models our approach is more scalable to large object databases than traditional methods. To demonstrate the utility of this approach, we train our system to recognize any of 50 objects in everyday cluttered scenes with substantial occlusion. Without further optimization we also demonstrate near-perfect recognition on a standard 3-D recognition problem. Our system has an interpretation as a sparsely connected feed-forward neural network, making it a viable model for fast, feed-forward object recognition in the primate visual system.
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Placement driven retiming with a coupled edge timing model
(2001)
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Ingmar Neumann
Wolfgang Kunz
- Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the predicted performance improvement will still be valid after placement has been performed. This paper presents a new retiming algorithm using a highly accurate timing model taking into account the effect of retiming on capacitive loads of single wires as well as fanout systems. We propose the integration of retiming into a timing-driven standard cell placement environment based on simulated annealing. Retiming is used as an optimization technique throughout the whole placement process. The experimental results show the benefit of the proposed approach. In comparison with the conventional design flow based on standard FEAS our approach achieved an improvement in cycle time of up to 34% and 17% on the average.
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LOT: Logic Optimization with Testability - new transformations for logic synthesis
(1998)
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Mitrajit Chatterjee
Dhiraj K. Pradhan
Wolfgang Kunz
- A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools.
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Accelerating Boolean implications with FPGAs
(1999)
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Kolja Sulimma
Dominik Stoffel
Wolfgang Kunz
- We present the FPGA implementation of an algorithm [4] that computes implications between signal values in a boolean network. The research was performed as a masterrsquos thesis [5] at the University of Frankfurt. The recursive algorithm is rather complex for a hardware realization and therefore the FPGA implementation is an interesting example for the potential of reconfigurable computing beyond systolic algorithms. A circuit generator was written that transforms a boolean network into a network of small processing elements and a global control logic which together implement the algorithm. The resulting circuit performs the computation two orders of magnitudes faster than a software implementation run by a conventional workstation.
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Convergence behaviour of structural FSM traversal
(2000)
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Dominik Stoffel
Wolfgang Kunz
- We present a theoretical analysis of structural FSM traversal, which is the basis for the sequential equivalence checking algorithm Record & Play presented earlier. We compare the convergence behaviour of exact and approximative structural FSM traversal with that of standard BDD-based FSM traversal. We show that for most circuits encountered in practice exact structural FSM traversal reaches the fixed point as fast as symbolic FSM traversal, while approximation can significantly reduce in the number of iterations needed. Our experiments confirm these results.
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An exact algorithm for solving difficult detailed routing problems
(2001)
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Kolja Sulimma
Wolfgang Kunz
- Channel routing is an NP-complete problem. Therefore, it is likely that there is no efficient algorithm solving this problem exactly.In this paper, we show that channel routing is a fixed-parameter tractable problem and that we can find a solution in linear time for a fixed channel width.We implemented our approach for the restricted layer model. The algorithm finds an optimal route for channels with up to 13 tracks within minutes or up to 11 tracks within seconds.Such narrow channels occur for example as a leaf problem of hierarchical routers or within standard cell generators.
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Tight coupling of timing driven placement and retiming
(2001)
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Ingmar Neumann
Wolfgang Kunz
- Retiming is a widely investigated technique for performance optimization. In general, it performs extensive modifications on a circuit netlist, leaving it unclear, whether the achieved performance improvement will still be valid after placement has been performed. This paper presents an approach for integrating retiming into a timing-driven placement environment. The experimental results show the benefit of the proposed approach on circuit performance in comparison with design flows using retiming only as a pre- or postplacement optimization method.
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Verification of integer multipliers on the arithmetic bit level
(2001)
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Dominik Stoffel
Wolfgang Kunz
- One of the most severe short-comings of currently available equivalence checkers is their inability to verify integer multipliers. In this paper, we present a bit level reverse-engineering technique that can be integrated into standard equivalence checking flows. We propose a Boolean mapping algorithm that extracts a network of half adders from the gate netlist of an addition circuit. Once the arithmetic bit level representation of the circuit is obtained, equivalence checking can be performed using simple arithmetic operations. Experimental results show the promise of our approach.
