TY  - JOUR
A1  - Grabowski, Darius
A1  - Platte, Daniel
A1  - Hedrich, Lars
A1  - Barke, Erich
T1  - Time constrained verification of analog circuits using model-checking algorithms
T2  - Electronic notes in theoretical computer science
N2  - In this contribution we present algorithms for model checking of analog circuits enabling the specification of time constraints. Furthermore, a methodology for defining time-based specifications is introduced. An already known method for model checking of integrated analog circuits has been extended to take into account time constraints. The method will be presented using three industrial circuits. The results of model checking will be compared to verification by simulation.
KW  - Model Checking
KW  - Analog Circuits
KW  - CTL
KW  - Time Constraints
Y1  - 2006
UR  - http://publikationen.ub.uni-frankfurt.de/frontdoor/index/index/docId/76264
UR  - https://nbn-resolving.org/urn:nbn:de:hebis:30:3-762646
SN  - 1571-0661
VL  - 153
IS  - 3
SP  - 37
EP  - 52
PB  - Elsevier
CY  - Amsterdam
ER  -