TY  - CONF
A1  - Hartje, Hendrik
A1  - Neumann, Ingmar
A1  - Stoffel, Dominik
A1  - Kunz, Wolfgang
T1  - Cycle time optimization by timing driven placement with simultaneous netlist transformations
T2  - Proc. of the IEEE International Symposium on Circuits and Systems, (ISCAS) Feb. 5-9 2001, Sydney, Australia
N2  - We present new concepts to integrate logic synthesis and physical design. Our methodology uses general Boolean transformations as known from technology-independent synthesis, and a recursive bi-partitioning placement algorithm. In each partitioning step, the precision of the layout data increases. This allows effective guidance of the logic synthesis operations for cycle time optimization. An additional advantage of our approach is that no complicated layout corrections are needed when the netlist is changed.
Y1  - 2006
UR  - http://publikationen.ub.uni-frankfurt.de/frontdoor/index/index/docId/2894
UR  - https://nbn-resolving.org/urn:nbn:de:hebis:30-25185
SN  - 0-7803-6685-9
SP  - V-359
EP  - V-362
ER  -