TY  - JOUR
A1  - Chatterjee, Mitrajit
A1  - Pradhan, Dhiraj K.
A1  - Kunz, Wolfgang
T1  - LOT: Logic Optimization with Testability - new transformations for logic synthesis
T2  - IEEE Transactions on Computer Aided Design
N2  - A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools.
KW  - ATPG
KW  - built-in self-test
KW  - logic synthesis
KW  - optimization
KW  - testability
Y1  - 2006
UR  - http://publikationen.ub.uni-frankfurt.de/frontdoor/index/index/docId/2879
UR  - https://nbn-resolving.org/urn:nbn:de:hebis:30-25271
VL  - 17
IS  - 5
SP  - 386
EP  - 399
ER  -