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A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools.
We present the FPGA implementation of an algorithm [4] that computes implications between signal values in a boolean network. The research was performed as a masterrsquos thesis [5] at the University of Frankfurt. The recursive algorithm is rather complex for a hardware realization and therefore the FPGA implementation is an interesting example for the potential of reconfigurable computing beyond systolic algorithms. A circuit generator was written that transforms a boolean network into a network of small processing elements and a global control logic which together implement the algorithm. The resulting circuit performs the computation two orders of magnitudes faster than a software implementation run by a conventional workstation.
We present a theoretical analysis of structural FSM traversal, which is the basis for the sequential equivalence checking algorithm Record & Play presented earlier. We compare the convergence behaviour of exact and approximative structural FSM traversal with that of standard BDD-based FSM traversal. We show that for most circuits encountered in practice exact structural FSM traversal reaches the fixed point as fast as symbolic FSM traversal, while approximation can significantly reduce in the number of iterations needed. Our experiments confirm these results.
Channel routing is an NP-complete problem. Therefore, it is likely that there is no efficient algorithm solving this problem exactly.In this paper, we show that channel routing is a fixed-parameter tractable problem and that we can find a solution in linear time for a fixed channel width.We implemented our approach for the restricted layer model. The algorithm finds an optimal route for channels with up to 13 tracks within minutes or up to 11 tracks within seconds.Such narrow channels occur for example as a leaf problem of hierarchical routers or within standard cell generators.
Retiming is a widely investigated technique for performance optimization. In general, it performs extensive modifications on a circuit netlist, leaving it unclear, whether the achieved performance improvement will still be valid after placement has been performed. This paper presents an approach for integrating retiming into a timing-driven placement environment. The experimental results show the benefit of the proposed approach on circuit performance in comparison with design flows using retiming only as a pre- or postplacement optimization method.
One of the most severe short-comings of currently available equivalence checkers is their inability to verify integer multipliers. In this paper, we present a bit level reverse-engineering technique that can be integrated into standard equivalence checking flows. We propose a Boolean mapping algorithm that extracts a network of half adders from the gate netlist of an addition circuit. Once the arithmetic bit level representation of the circuit is obtained, equivalence checking can be performed using simple arithmetic operations. Experimental results show the promise of our approach.
This paper presents a new timing driven approach for cell replication tailored to the practical needs of standard cell layout design. Cell replication methods have been studied extensively in the context of generic partitioning problems. However, until now it has remained unclear what practical benefit can be obtained from this concept in a realistic environment for timing driven layout synthesis. Therefore, this paper presents a timing driven cell replication procedure, demonstrates its incorporation into a standard cell placement and routing tool and examines its benefit on the final circuit performance in comparison with conventional gate or transistor sizing techniques. Furthermore, we demonstrate that cell replication can deteriorate the stuck-at fault testability of circuits and show that stuck-at redundancy elimination must be integrated into the placement procedure. Experimental results demonstrate the usefulness of the proposed methodology and suggest that cell replication should be an integral part of the physical design flow complementing traditional gate sizing techniques.
n this paper we report on the investigation of baryonic resonance production in proton-proton collisions at the kinetic energies of 1.25 GeV and 3.5 GeV, based on data measured with HADES. Exclusive channels npπ+ and ppπ0 as well as ppe+e− were studied simultaneously in the framework of a one-boson exchange model. The resonance cross sections were determined from the one-pion channels for Δ(1232) and N(1440) (1.25 GeV) as well as further Δ and N* resonances up to 2 GeV/c2 for the 3.5 GeV data. The data at 1.25 GeV energy were also analysed within the framework of the partial wave analysis together with the set of several other measurements at lower energies. The obtained solutions provided the evolution of resonance production with the beam energy, showing a sizeable non-resonant contribution but with still dominating contribution of Δ(1232)P33. In the case of 3.5 GeV data, the study of the ppe+e− channel gave the insight on the Dalitz decays of the baryon resonances and, in particular, on the electromagnetic transition form-factors in the time-like region. We show that the assumption of a constant electromagnetic transition form-factors leads to underestimation of the yield in the dielectron invariant mass spectrum below the vector mesons pole. On the other hand, a comparison with various transport models shows the important role of intermediate ρ production, though with a large model dependency. The exclusive channels analysis done by the HADES collaboration provides new stringent restrictions on the parameterizations used in the models.
his contribution aims to give a basic overview of the latest results regarding the production of resonances in different collision systems. The results were extracted from experimental data collected with HADES that is a multipurpose detector located at the GSI Helmholtzzentrum, Darmstadt. The main points discussed here are: the properties of the strange resonances Λ(1405) and Σ(1385), the role of Δ’s as a source of pions in the final state, the production dynamics reflected in form of differential cross sections, and the role of the ϕ meson as a source for K− particles.